Job Description

Minimum qualifications: Bachelor\'s degree in Computer Science, Electrical Engineering, or equivalent practical experience. 10 years of experience working on multiple SoCs with silicon success. Experience with Verilog or System verilog language. Experience in high performance design, multi-power domains with clocking. Preferred qualifications: Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip level verification. Domain knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing. Proficient with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation. About the job Our computational challenges are so big, complex and unique we can\'t just purchase off-the-shelf hardware, we\'ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google\'s services. As a Hardware Engineer, you design and build the systems that are the heart of the world\'s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users. With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors. Google\'s mission is to organize the world\'s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people\'s lives better through technology. Responsibilities Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc. Perform RTL coding for SS/SOC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks. Work with key design collaterals such as SDC and UPF. Work with stakeholders to discuss the right collateral quality and identify solutions/workarounds. Interact closely with the architecture team and develop implementation (microarchitecture and coding) strategies to meet quality, schedule, and PPA for Sub-system/chip-level integration.

foundit