Job Description

In this position, the candidate will play a senior Technical Leadership role in the Server microarchitecture and Logic Design/Integration for SoC products designed by Xeon Engineering Group within the Design Engineering Group/Data Center and AI business Unit.

The candidate is expected to actively collaborate and drive the development of Micro-architecture specifications and the design implementation for Xeon Server SoCs

Candidate responsibilities include the following:

• Lead a team of engineers to successfully deliver design from architecture to tape out.
• All phases of front end design including micro-architectural design and specification.
• Perform logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and subsystems for inclusion in full chip designs.
• Work with architects on feature scoping and approvals, feasibility studies, design tradeoff analysis, IP Vendor selection.

- Staging plan development, Design and Testplan Reviews, Interface with - - Physical Design for timing/clocking issues, CCB, PNP, and post-Silicon debug lead.

• Close collaboration with debug (DFD) and manufacturing (DFT) teams in incorporating the uArch and design requirements
• Close collaboration with planning teams, architects, validation and physical design teams.
• Drive resolution of technical issues with IP and SOC development teams to meet schedule and quality.
• Drive and help build forward looking strategy for the team
• Mentor aspiring leads in the logic design team and build a strong technical bench strength

Qualifications
Required Educational Qualification

• Bachelor's degree in electrical engineering or associated discipline with 12+ years of experience or,
• Master's degree in electrical engineering or associated discipline with 10+ years of experience

Minimum Required Qualifications:

• 7 plus years of experience with IP / ASIC design / validation in Front End processes including RTL development, functional and performance verification.
• 5 plus years of experience in design, development, and integration of design blocks (IP) for system-on-chip (SoC) components.
• Experience in Verilog and System Verilog based logic design.
• Experience in Perl and/or C++ programming is an added advantage
• 5 plus years of experience in synthesis flow and timing closure.
• Experience in Xeon SoC/IP design and integration is an added advantage
• Knowledge of considerations for performance, power and cost optimization.

The candidate should exhibit:

• Excellent communication skills
• Flexibility to work in a dynamic environment and seamlessly multitask
• Acumen to identify develop strategic opportunities
• Proactive drive to achieve high-quality results through strong team-work
• Innovative thinker able to propose/drive solutions to tough product definition challenges to meet power/performance and functional requirements
• Proven ability to drive solutions to complex cross-functional technical problems working with senior technical peers/partner organizations
• Solid breadth of design expertise spanning all phases of the design cycle

Inside this Business Group
Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.
Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
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