Job Description

Staff Semiconductor Design Engineer, DFT and SynthesisWe are Aptiv - a global technology company with 190,000 specialists in 46 countries. We develop innovative software and build the hardware to bring autonomous driving cars, advanced driver-assistance systems, connected vehicles and smart cities to life in a way that only we can. We work in partnership with almost all car manufacturers. Our sensors, systems and software can already be found in almost all passenger cars today.With our deep domain expertise, Aptiv is developing solutions that solve our customers\' toughest challenges. We are enabling the transition to software-defined vehicles supported by electrified and intelligently connected architectures \xe2\x80\x93 which will combine to power the future of mobility.Aptiv\xe2\x80\x99s custom silicon management group provides critical custom Silicon for all Aptiv products including Autonomous Driving, ADAS, Infotainment, Zonal Control, and others. This team translates the system requirements of Aptiv\xe2\x80\x99s next-generation products into the SOC/IC requirements and architectural design, then manages the technical performance of external SOC/IC design partners who design the custom silicon SOCs/ICs for use in Aptiv\xe2\x80\x99s products.We are looking for a senior staff design engineer to work closely with multiple engineering teams who are focused on the development of Aptiv\xe2\x80\x99s future generation of products.This role is based in Aptiv\xe2\x80\x99s Bangalore, India office.Your Role:

• Develop SoC Design and verification for Clock/JTAG/Analog/DFT IP Scan Insertion, ATPG, scan verification and pattern generation.
• Perform RTL Synthesis to achieve the best Performance/Power/Area of the designs, DFT insertions that include MBIST and SCAN, setup.
• Develop Compressor based Scan chain insertion.
• BSCAN structure insertion based on the IEEE 1149.1 & 1149.6 standards.
• Logic BIST implementation for the Self-test capability.
• Memory BIST insertion, validation and pattern generation.
• Analog BIST implementation for selected analog blocks like PLLs, ADC & DACs.
• IO Bist methods implementation for IO structures of the SOCs.
• Timing Constraints for functional and Test Modes, and Validation.
• Create Power Intent for the designs and verify power intent on RTL, run static
• Low-Power checks on gate level netlists, Verify Logic Equivalency.
• Analysis of Functional Design for Testability, including product functionality and access through external connections, BIST and Board Level Diagnostics, control of significant circuits, and isolation of functional blocks for testing.
• Create and maintain DFT timing constraints.
• Checks between RTL to Gates and Gates to Gates, setup signoff
• Static Timing Analysis and ECO flows and achieve timing closure working with the Design/DFT/PD teams, run Power.
• SoC DFT architecture specification including test muxing and DFT RTL coding, IEE1149.1 Boundary Scan design.
• Functional Pattern generation.
• Pattern debug on ATE.
• Design Verification for DFT.
• Analysis and estimate power at RTL level, run Sign off Power.
• Analysis on the P&R data, support the DV team to enable gate level simulations with SDF and UPF aware simulations, and support functional eco rollout with automated ECO flows.

Your Background:

• Master\xe2\x80\x99s degree in electrical engineering, computer engineering or equivalent.
• 8+ years of experience with ARM CPU based ASIC/SOC design.
• Review implemented efficient DFT methodologies to enhance test coverage and minimize test time.
• Design, implement, and verify Memory Built-In Self-Test (MBIST) solutions for various memory types.
• Conduct DFT simulations and analyses to identify and address potential testability issues.
• Work closely with SOC implementation design teams to optimize test points and facilitate the generation of test patterns.
• Collaborate with manufacturing teams to ensure seamless transfer of test solutions to production.
• Debug and resolve any DFT-related issues that arise during the testing phase.
• Stay current with industry trends and advancements in DFT and MBIST technologies.
• Synthesis & STA engineers will perform RTL Synthesis to achieve the best Performance/Power/Area of the designs, DFT insertions that include MBIST and SCAN, setup
• Timing Constraints for functional and Test Modes, and Validation.
• Candidates will create Power Intent for the designs and verify power intent on RTL, run static
• Low-Power checks on gate level netlists, Verify Logic Equivalency
• Checks between RTL to Gates and Gates to Gates, setup signoff
• Static Timing Analysis and ECO flows and achieve timing closure working with the Design/DFT/PD teams, run Power
• Analysis and estimate power at RTL level, run Sign off Power
• Analysis on the P&R data, support the DV team to enable gate level simulations with SDF and UPF
• Strong experience with emulation platforms (e.g., ZeBu, Palladium, and other FPGA base emulators).
• Strong experience with Verilog, System Verilog.
• Strong Experience in Tcl, Perl, Python scripting.
• Strong written and verbal communication skills.
• It\xe2\x80\x99s a plus if you have automotive design experience.

Why join us?

• You can grow at Aptiv. Whether you are working towards a promotion, stepping into leadership, considering a lateral career move, or simply expanding your network \xe2\x80\x93 you can do it here. Aptiv provides an inclusive work environment where all individuals can grow and develop, regardless of gender, ethnicity or beliefs.
• You can have an impact. Safety is a core Aptiv value; we want a safer world for us and our children, one with: Zero fatalities, Zero injuries, Zero accidents.
• You have support. Our team is our most valuable asset. We ensure you have the resources and support you need to take care of your family and your physical and mental health with a competitive health insurance package.

Your Benefits at Aptiv:

• Hybrid and flexible working hours;
• Higher Education Opportunities (UDACITY, UDEMY, COURSERA are available for your continuous growth and development);
• Life and accident insurance;
• Sodexo cards for food and beverages
• Well Being Program that includes regular workshops and networking events;
• EAP Employee Assistance;
• Access to fitness clubs (T&C apply);
• Creche facility for working parents;

Apply today, and together let\xe2\x80\x99s change tomorrow!#LI-PG1Privacy Notice - Active Candidates:Aptiv is an equal employment opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, sex, gender identity, sexual orientation, disability status, protected veteran status or any other characteristic protected by law.

Aptiv