Job Description

[R&D Engineer, Staff] PD Methodology Expert Our Silicon Lifecycle Management (SLM) business is all about building next-generation intelligent in-chip sensors, hardware/software capabilities and analytics to integrate into technology products to manage and improve each semiconductor lifecycle stage. We offer the world\'s first full hardware IP, test, and end-to-end analytics to help customers integrate faster, optimize performance/power/area/schedule/yield, and enhance reliability. Meeting the unique challenges posed by various target applications, SLM enables differentiated products to market quickly with reduced risk. Job Overview Part of the rapidly expanding Hardware-Analytics and Test (HAT) business unit, R&D Engineer, Staff. This technical role is responsible for HDG\'s (Hardware Development Group) Physical Design methodology setup to ensure overall productivity improves in terms of cycle time and man-months for the Silicon Lifecycle management Ips. This includes ensuring automated (synopsys EDA flow based) flow setup for SLM IP blocks with appropriate backend flow. The person need to be a expert of physical design with innovative mindset and automation skills. Work will include working with Analog and Digital teams together for setting up the right PD methodology for both Front end and backend. Responsibilities and Duties Responsible for Physical design for MSIPs for appropriate methodology Hands on with custom automations around Synopsys EDA flow PD Work out innovative design methodologies to overcome challenges Understand AMS Ips and ensure best cycle time for execution by enabling backend flow Analyse pros and cons of different flow for IP integration and customer SOC flow Qualifications BS or MS degree in Electrical Engineering/Computer Science/Computer Engineering. 8 to 11 years of experience in the fields of Analog/Mixed Signal design for leading edge technologies Innovation mindset with automation in SKILL , Perl , Python , C++ Deep expertise with Synopsys backend flow Ability to work with cross functional team spread across different geographies. Preferred Skills Demonstrated experience with Physical Design and methodology expertise Understanding latest foundry PDKs and their technical collaterals as required by the Physical design teams including their usage in design and layout Thorough knowledge of Physical design flow with digital top SOC integration methodology Closely work with Analog layout team by reviewing and enabling Layout methodology (automations) for Analog+Digital integration Location: To be hired for Bangalore or Bhubaneswar ABOUT US Synopsys, Inc. (Nasdaq:SNPS) is the Silicon to Software partner for creative companies developing the electronic products and software applications we rely on every single day. As the world\'s 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software quality and security solutions. Whether you\'re a system-on-chip (SoC) designer building advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver exceptional, secure products for the era of connected everything. The company is headquartered in Mountain View, California, and has approximately 113 offices located throughout North America, South America, Europe, Japan, Asia and India. Since 1986, Synopsys has been at the heart of accelerating electronics innovation with engineers around the world having used Synopsys technology to successfully design and create billions of chips and systems that are found in the electronics that people rely on every single day.

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