Job Description

At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're pow

At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. R&D Engineer, Sr I Responsibilities: Develop CMOS embedded memories such as SP SRAM, DP SRAM, Register File, and ROM: Design architecture and circuit implementation, especially ultra high speed, ultra low power, or high density design portfolio. Perform schematic entry, circuit simulation, layout planning, layout supervision, design verification and validation. Interface with CAD and Frontend engineers for memory compiler automation, EDA model generation and full verification flow. Perform bit cell development and bit cell verification, and drive physical layout design and verification. Provide support and/or perform other duties as assigned and required Authority: Schedule own work flow Normally receives little instruction on day-to-day work, general instructions on new assignments. Demonstrates good judgment in selecting methods and techniques for obtaining solutions. Skills Requirements: Bachelor's or Master's degree, Electrical Engineering, Telecommunication or related fields 5-8 years' experience in embedded CMOS memory development at advanced technology nodes Hands-on embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation. 6T and 8T SRAM bit cells design, SRAM failure analysis, memory testing methodology and strong data analysis skills. Proficient with CMOS memory design, circuit simulation, memory layout designs, layout parasitic extraction and knowledge of layout verification tools and debugging techniques. Experience in depth analysis on memory bit cell read/write/hold margin and reliability risk. Programming capability- C-Shell, Perl. C++ or Java script a plus Excellent analytical and problem solving skills along with attention to details. Can develop a document, report or presentation for a range of tasks Microsoft Office: Word, Excel, PowerPoint, Shared point and Outlook Self-motivated, self-directed, detailed oriented and well organized Good analytical, problem solving and negotiation skills Ability to lead/mentor trainees and junior engineers as well as lead and manage projects. A strong command of English both verbal and written Strong interpersonal communication and team working skills Professionalism, Critical/Logical thinking, future goals focused High commitment to continuous learning Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.