Job Description

40240BR
INDIA - Noida
and Requirements
You will be part of an excellent development team in the area of System Level Design for Architecture exploration and Software Development. The role is for a senior R&D engineer with a focus on micro-architecture and Verilog/SystemVerilog RTL expertise to meet Performance, Power and Area specification of targeted design at system level architecture in semi-conductor design industry. You will be part of the team leading the innovation edge for design and development of tools, algorithms, flows and methodologies. The role will involve multi-disciplinary skills and learning from the area of Verilog/SystemVerilog/VHDL for design and verification clubbed with semi-conductor design from front end design to implementation.
We are looking for a dynamic, passionate and self-motivated person with excellent experience in the field of RTL (Verilog/SytemVerilog/VHDL). The person should be willing to apply their understanding and learning to a completely new domain. The person will be responsible for understanding and developing RTL IPs and SoC designs, enable rational and efficient RTL code generation and verification through multiple static and formal tools, creating applications and developing algorithms that can be applied on the RTL for basic SW bring-up. The role involves creating path breaking innovative technologies with ample opportunity for publications and patents which is the DNA of the team.
We offer an international work environment that is characterized by flexibility, an informal atmosphere, a fast pace environment and an opportunity to impact the way the industry develops new systems. You will work with highly professional and motivated colleagues who value and support your contribution. Synopsys is a dynamic international workplace with opportunities for personal and professional growth. The position holds an attractive compensation and benefits package commensurate with a results-oriented global company.
As a senior member of the product R&D team in Synopsys, you will be responsible for

• Development and enhancements of RTL and Verilog features, flows and solutions
• Quality execution of software development projects, taking responsibility for designing, developing, troubleshooting, or debugging software programs
• Creation of reliable plans and effort estimates for your projects.
• Focus on innovation to ensure continuous product enhancements.

Education
BE / B. Tech / M.Tech in Computer Science or Electronics

Experience
5-7 years

Technical Skills
Essential:

• Proficient and extensive experience with Verilog/SystemVerilog/VHDL for design and verification
• Proficient in micro-architecture and Verilog/SystemVerilog RTL to meet Performance, Power and Area specification of targeted design
• Support Design, Verification and Validation flow of SoCs or IPs using Synopsys tool such as VCS, Verdi etc.
• Perform RTL design and Verification of digital macros as per architectural description of SoC
• Run Lint/CDC and other tools to check the quality of the IP/SoC
• Developing design, verification and validation tool flows as per customer project requirement
• Work with implementation team to synthesize and place/route the synthesized netlist and also assess timing report etc.
• Evaluate and identify bottlenecks in design and provide feedback on micro-architecture, pipelining, IP stitching etc.
• Familiar with ARM Design architecture and SoC design flow
• Good hands-on experience with Scripting (TCL, Python, Shell, perl, etc), and C/C++ based software development
• Excellent problem solving skills and ability and attitude to brainstorm and create solutions where none exist
• Proven background in OOP, data structure, algorithms, and programming concepts
• Good investigation and problem-solving skills
• Excellent desires to learn and explore new technologies

Desirable:

• Experience in EDA domain
• SoC architecture understanding
• Basic understanding of various peripheral interfaces such as UART, SPI, I2C etc.
• Basic Understanding of AMBA Bus Protocol such as AXI3/AXI4/APB/AHB etc.
• Design knowledge of one/more industry standard bus interfaces (PCIe, SPI, SRIO, USB, XAUI ) and memory interfaces (DDR2, DDR3 etc.)
• Experience in interfacing with architecture and Physical implementation teams is a plus
• Interacting closely with SW teams for tool flow setup from Digital Design and verification perspective.
• Work with SW team for analysing and stitching various digital IP’s in Synopsys Tool flow for verification
• Exposure to Linux and Windows platforms
• Well versed with Software Engineering and agile development processes

Personal Attributes

• High energy person with the ability to go an extra mile.
• A proactive team player with good written and verbal communication skills.
• Creative and flexible personality.

Job Category
Engineering
Country
India
Job Subcategory
R&D Engineering
Hire Type
Employee