Job Description

40595BR
INDIA - Bangalore
and Requirements
The Circuit STA Timing Generation Manager will be responsible for delivering best quality custom circuit timing models to the place and route (P&R) team. This position requires hands on experience with static timing analysis (STA) tools and flows (Prime-Time, NanoTime) with some knowledge of mixed signal circuit design principles. The responsibilities include, apart from managing a timing team, delivering timing models, improving our STA flow, identifying design vs flow issues, working closely with cross functional teams to control quality of internal timing and solving any issues at the interface between mixed signal circuit and P&R digital hardware.
This position is also responsible for black box extraction, timing characterization of analog circuit within black box, developing and maintaining timing constraints for STA flow on mixed signal circuits, evaluating and fixing timing violations, closing circuit level internal timing, timing correlation between STA and extraction tools, participate/contribute in timing expert meetings/reviews and publishing timing status after each milestones with quality checks. This position requires strong scripting skills to automate checks and the ability to lead and train junior engineers to become experts in timing.

Required:
MSEE and 10 years relevant experience preferred (or equivalent education and experience).
Solid understanding of static timing concepts and engineering fundamentals.
Strong expertise in transistor-level design simulation/verification (HSPICE/Finesim) to debug circuit level issues with waveforms.
Experienced in physical verification to debug LVS issues at block and top level.
Experienced in STAR or similar extractor to debug extraction issues.
Good understanding of hierarchical design, black-box, and selected nets extractions.
Strong skills with Synopsys Prime-Time.
Experience in advanced technology nodes preferred.
Good knowledge of TCL, Perl and other scripting languages.
Good communication and interpersonal skills.
Plus:
Transistor based STA experience.
Silicon-Smart experience highly desirable.
NanoTime experience highly desirable.
CCS/LVF timing and noise model generation experience.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Job Category
Engineering
Country
India
Job Subcategory
Analog Design
Hire Type
Employee