Job Description

At Microchip, we work every day to innovate and develop products that solve our customers’ technology challenges. Our team of more than 20,000 people worldwide is dedicated to delivering on the promise of working together to improve lives.
Learn about our
guiding values that are the building blocks and foundation of our culture and discover how we make a positive impact in the communities in which we operate. We believe our culture fosters trust, collaboration and belonging.
Our people serve the industrial, computing, automotive, communications, aerospace and defense, and consumer market segments. As part of our global team, you can build technology solutions in our six growth areas – 5G, data centers, autonomous driving, the Internet of Things, electric vehicles, and artificial intelligence and machine learning.
Around the world, we are committed every day to recruiting, retaining and promoting people in our diverse workforce. Your perspective, passion and ingenuity will contribute to achieving more as we fulfill our
mission as a leading provider of smart, connected and secure embedded control solutions.
Join our community of exceptional people doing incredible things.
:
As part of Timing and Communications Group (TCG) the candidate will set the seed for TCG Design Center in Bangalore India. The self-motivated and highly creative Candidate shows strong Technical Lead to resolve independently any issues during IC development both at Product and Process levels. The Candidate has strong Communication skills to interface with various other groups like Architecture, Digital Back-End, Characterization, Test and Product Engineering. The innovative Analog circuit solutions enable clocks with highly stable timing (Ultra-Low Jitter: ULJ) or very low current consumption (Ultra-Low Power: ULP) as key performances in IC Products like MEMS-XTAL Oscillators, Clock Generators and Clock Distribution IC Products. Key Timing ICs technology comprises Oscillators, duty-cycled Incremental Analog-to-Digital Converters and Temperature Sensors, ULP / ULJ Fractional Dividers, Analog and Digital PLL’s, Frequency Synthesizer.

Duties include:

Work with Application, Architects, Characterization, Test and Product engineers
Detailed Circuit Designs of Analog circuits (PLL or other clock circuits) with Spectre / APS tools under Cadence ADE-L / -XL
Verilog / Verilog-AMS modeling and Full Chip functional verification thru AMS mixed-mode simulations
Knowledgeable to work with digital engineer to get Digital Implementation of Algorithms (Filters, Calibration and Temp Compensation in RTL-code)
Detailed elaboration of Timing constraints interfacing with Corporate Digital Team for Place and Route
Floor planning of Timing SOC chip including Analog and Digital IP Macros
Management of the Full Chip Physical Layout Detailed Design and Verification with Mentor Caliber Tools for DRC / LVS / ERC
Variations aware Mixed-Signal Full Chip verification with Manufacturing yield analysis
Hands-on bench test and device characterization in the Lab to debug and support validation.

Requirements/Qualifications:
3-5 years’ experience of Analog Design Experience
Self-motivated, able to work independently, excellent communication skills, excellent presentation skills for design reviews and ability to excel in a multi-disciplinary team environment across multiple locations
Strong analytical, and problem-solving skills, as well as hands-on SoC debugging / bring up skills
Expert in Analog CMOS circuit design and associate requirements for ULP and ULJ solutions
Very good understanding of Analog IP macros such as XO, PLL, DLL, Voltage Regulator, Bandgap, Comparator, others …
A deep knowledge of transistor operation and their physical Models
Strong intuitive and analytical understanding of transistor-level design including stability, matching, transient and noise analysis, low power design trade-offs, and architectural and systems issues
Experience in high-level modeling using Verilog-AMS and writing Verilog RTL code
Experience with Advanced Circuit simulation and Mixed-Signal (AMS) CAD tools including Process Variations aware flows and Layout Parasitic
Experience with Layout Design Tools (Virtuoso) and Verification Tools (Caliber)
Good understanding of Digital Flow including Synopsys Tools like DC, FM and PT
Lab experience with test setup, measurement and excellent debugging and problem-solving skills

Travel Time:
0% - 25%