Job Description

The General-Purpose Microcontroller Sub-Group (GPM) is the largest division at ST Microelectronics and the world leader in the microcontroller market supported by our STM32 products.
Leader in the Internet of Things market which is a rapidly expanding sector driven by strong growth, GPM Division asserts its ambition in the Microcontroller market (STM32) by continuing to innovate and to bring tomorrow's solutions.
Passionate & motivated join our team of state of the art engineers.

Role & Responsibility :
As CAD Engineer, you'll be responsible to generate & validate the EDA views & Methodologies for Foundation IPs & complex Analog-Mixed Signal macros (including IPs sourced through external vendors) for smooth integration in full SOC flow used by STM32 products. It includes:

- Generation & validation of EDA views and associated methodologies for Foundation IPs & Macros. It als
- Understand with the IP design experts to the IP design & specification (more in electrical characteristics and functional aspect).
- interact and works with EDAs especially in domain such as analog/digital Characterization, P&R tooling, Analog/Digital simulation, Timing/Power Analysis flows and Signal Integrity.

You'll be working in an empowered environment with state of the art methodologies and tools, to contribute to STM32 worldwide success.
A multicultural environment and its diversity are the strength of our dynamic team. A structured development plan will evolve with you along all your career.
We are looking for people with enthusiasm, constantly curious and creative towards continuous innovation, with good communication skills.
Join & Grow with us!

Profile
Educational Qualification :
Bachelors/Masters in Electronics/Electrical Engineering

Technical Skills/Knowledge Requirements :
- Good understanding of digital design concepts & CMOS fundamentals.

- Can quickly understand the functional & electrical specifications of custom/full custom IPs.
- Understating of IO/Standard cells/Memories Characterization flow using industry standard tools like Kronos/Liberate/Silicon Smart etc.
Good understanding of static timing analysis concepts using PT or equivalent EDA tools.
- Good understanding of various formats of liberty files (NLDM, CCS, LVF, APL etc.).
- Basic understanding of Layout / Schematic view and associated tooling such as Virtuoso or Custom Complier.
- Able to write basic HDL models (Verilog/VHDL) and associated test bench for validation.

Personality & Soft Skill Requirements :
- Good communication and interpersonal skills.
- Excellent team player & collaborative attitude
- Passionate and motivated to make a difference
- Proactive, Enthusiastic, Creative & Innovative
Education: Any Graduate
Industry: Telecom, IT-Hardware/Networking

Skills Required