Job Description

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

SMTS Silicon Design Engineer
The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc . The candidate will also be responsible for additional tasks that are related to SOC design closure.

REQUIREMENTS:
Bachelor/Master Degree in Electronics Engineering and at least 10 years experience in complex ASIC Design projects.
Have in depth knowledge of entire physical design process from floorplan till GDS generation
Good Exposure to Physical Verification Process
Have hands-on experience in latest deep-sub-micron technologies 14nm and below
Hands on experience in PnR tools Synopsys ICC/Cadence Encounter etc.
Experience in low power designs and handling congestion or timing critical tiles will be preferred
Should be a quick learner and have good attention to detail
Experience in ECO implementation preferred
Scripting skills in Perl/Python etc.
Must have good communication & problem-solving skills.
Should be able to handle PnR tasks with minimal supervision
Should be able to lead a small team technically and drive the assigned tasks to closure

Desired Skills:
1. SoC implementation expertise. Multimillion gates integration.
2. Physical Synthesis, Constraints validation.
3. Floorplanning, Power planning.
4. Scan Synthesis, Scan re-order.
5. Static Timing analysis (STA).
6. Analysis: IR, EM, Noise.
7. Physical Verification.
Education: Any Graduate
Industry: IT-Hardware/Networking

Skills Required