Job Description

The General-Purpose Microcontroller Sub-Group (GPM) is the largest division at ST Microelectronics and the world leader in the microcontroller market supported by our STM32 products.
Leader in the Internet of Things market which is a rapidly expanding sector driven by strong growth, GPM Division asserts its ambition in the Microcontroller market (STM32) by continuing to innovate and to bring tomorrow's solutions.
Passionate & motivated join our team of state of the art engineers.

Role & Responsibility :
As Senior SOC FE Engineer, you'll be responsible for design and development of STM32 SOCs including:
- Design of SoC covering microarchitecture definition, digital solutions proposals meeting customers specification/requirements.
- SoC front-end development activities while closely engaging with other SOC teams like verification, DFT, physical implementation, etc.
- Delivery of SOC RTL, timing constraints, UPF & other collaterals to the SoC teams and support bringup across functions.
- SOC logic design like interconnect, controls, and interfaces.
- Engagement with product & system architecture teams to drive performance, area, and power optimization.
- Support to verification and silicon validation teams, and work with SW teams and occasionally with customers to support successful deployments.
- Maintenance of required documentation for SoC and/or SOC logic in accordance with the design quality requirement.

You'll be working in an empowered environment with state of the art methodologies and tools, to contribute to STM32 worldwide success.
A multicultural environment and its diversity are the strength of our dynamic team. A structured development plan will evolve with you along all your career.
We are looking for people with enthusiasm, constantly curious and creative towards continuous innovation, with good communication skills.
Join & Grow with us!

Profile
Educational Qualification :
Bachelors/Masters in Electronics/Electrical Engineering

Technical Skills/Knowledge Requirements :
- Extensive Design experience in SOC/IP development.
- Good understanding of SoC architecture preferably ARM based.
- Competence in digital design, RTL code development and simulation, chip-assembly flows, Timing Constraints, UPF, LINT, CDC analysis.
- Proficiency in bus protocols like AMBA AXI/AHB, and common communication protocols.
- Familiarity in complete implementation from SoC RTL to GDS, with good grasp of timing constraint definition for IP, subsystems and SoC, targeting performance, area, and timing optimization.
Education: Any Graduate
Industry: Telecom, IT-Hardware/Networking

Skills Required