Job Description

Sr. I R&D Engineer, Analog & Mixed Signal Layout - Our Silicon Lifecycle Management (SLM) business is all about building next-generation intelligent in-chip sensors, hardware/software capabilities and analytics to integrate into technology products to manage and improve each semiconductor lifecycle stage. We offer the world\'s first full hardware IP, test, and end-to-end analytics to help customers integrate faster, optimize performance/power/area/schedule/yield, and enhance reliability. Meeting the unique challenges posed by various target applications, SLM enables differentiated products to market quickly with reduced risk. s & Requirements Part of the rapidly expanding Hardware-Analytics and Test (HAT) business unit, an AMS Layout engineer works on the development of various Process, Voltage, Temperature and Current monitors as part of HDG (Hardware Development Group) product portfolio. As a full custom layout engineer, you will work closely with our mixed signal design engineers and CAD team to create floorplans and completing layout of state of the art SLM sensor IPs on most advanced process nodes (from 16nm down to 3nm and beyond). We are seeking an experienced, highly motivated and high-caliber individual to build these differentiating sensor products. This individual should have strong technical experience in full custom layout, backend implementation, timing, parasitic extraction, LVS and possess excellent project execution and planning skills. Job Requirements Automation focused and forward-looking thought process Sound knowledge of custom Analog/AMS design layout and backend implementation BS or MS degree in Electrical Engineering with 5+ years of relevant industry experience Knowledge of advanced process challenges, including ESD and Reliability Exposure to all, or parts of the entire design stack - device physics, fabrication technology, circuit design, standard cells, memory/hard macros, SOC integration Exposure to architecture, design and verification of PVT, Oscillators, Bandgap, PLLs, Amplifiers, PHYs and other Mixed-signal blocks Solid hands on experience with tools around LVS, DRC, post-layout simulations etc. Demonstrated experience with multiple CAD flows: design, verification, backend, validation, etc. Excellent teamwork, communication, mentoring and interpersonal skills with both internal teams and external customers Preferred skills : Skilled in layout of analog blocks using appropriate full custom layout techniques Strong understanding of SPICE simulator concepts and simulation methods Familiar with industry standard post-layout tools like Custom Compiler, StarRC, CalibrexRC, HSPICE, FineSim or equivalent Must have prior experience with Custom Compiler or equivalent schematic & Layout editor tools Experience with statistical design methodology like generating and analyzing Monte-Carlo results Experience in post-layout extraction & simulation, testing in conjunction with silicon validation Skilled in customer interactions and managing expectations, scope and requests Experience in PVT-sensors and/or DFT/DFx technologies is a strong plus At Synopsys, we\'re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we\'re powering it all with the world\'s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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