Job Description

Key Responsibilities:

Perform functional verification of IP or SoC-level designs using SystemVerilog and UVM methodologies Develop and maintain verification plans, testbenches, test cases, and coverage metrics Collaborate closely with design, architecture, and validation teams Debug RTL and testbench issues and work towards timely resolution Contribute to automation and continuous improvement of verification processes

Required Skills:

3 to 9 years of hands-on experience in SystemVerilog and UVM-based verification Strong understanding of IP/SoC-level verification techniques Solid debugging skills and familiarity with simulation tools (e.g., VCS, Questa, Incisive) Experience with scripting languages (e.g., Python, Perl, Shell) is a plus Good communication and teamwork skills
Job Type: Full-time

Pay: From ?1,000,000.00 per month

Benefits:

Commuter assistance Flexible schedule Health insurance Paid sick time Paid time off Provident Fund Work from home
Schedule:

Day shift
Supplemental Pay:

Performance bonus
Work Location: In person