Synthesis
Location: Bangalore
:
Power team, the engineer will be responsible for RTL power optimization, netlist power analysis, and optimization on novel machine learning and visual processor chips in advanced nodes.
1-3 years of relevant experience
Good understanding of timing constraints
Experience with RTL synthesis using tools such as Design Compiler (DC) and Genus
Experience in low-power design, tools, and methodologies including power intent (UPF) specifications is beneficial
Good understanding of ASIC design and physical design methodologies is beneficial
Experience (years) : 1-3 years
Education Qualification:
BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent
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