Job Description

I\'m hiring for RTL Verification/ RTL Design Engineer. If anyone interested please ping me directly or email your updated resume to [HIDDEN TEXT] Exp - 4- 15 Years Locations - Bangalore, Hyderabad. : As a member of our dynamic group, you will have the opportunity in Specify, design, developing and verifying Serdes/DDR/PCS RTL for low power and advanced mixed-signal circuit macro to be used in varies products from high performance data center to low power consumer SoCs. Good understanding of mixed signal concepts Good knowledge of RTL digital design fundamentals Deep knowledge of Verilog and System-Verilog Good understanding of front-end tools (Verilog simulators, linters, clock-domain crossing checkers) Working knowledge of synthesis, static timing, DFT is a huge plus good knowledge of System-Verilog assertions, checkers, scoreboard, and other design verification techniques Good knowledge of scripting languages. Perl and Python are plusses Good knowledge of Firmware, calibration, and adaptation Algorithm developments Strong communication and presentation skills and 3+ years of DDR/SERDES and supported protocols knowledge is a plus Candidate with the experience in one or more of Design or Verification below fields is preferred. You will be responsible for specifying and/or micro-architecting digital blocks in advanced mixed-signal circuits. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. Develop micro-architecture and test-chip/test-system specifications Work closely with the Controller and PCS design team Document the design for internal and external purposes, including maintaining PHY user guides Interface with customers and assist in integrating the IP Participate in all test chip and bring up activities Help improve RTL design and verification methodology Schedule and track the RTL development process. Provide regular status updates.

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