Job Description

The General-Purpose Microcontroller Sub-Group (GPM) is the largest division at ST Microelectronics and the world leader in the microcontroller market supported by our STM32 products.
Leader in the Internet of Things market which is a rapidly expanding sector driven by strong growth, GPM Division asserts its ambition in the Microcontroller market (STM32) by continuing to innovate and to bring tomorrow's solutions.
Passionate & motivated join our team of state of the art engineers.

Role & Responsibility :
As Senior SOC DFT Engineer, you'll be responsible for DFT of STM32 SOCs including:
- Meet the DFT/DFD/DFM (design for test / debug / manufacturability) requirements.
- DFT Architecture & Set up DFT flow, Scan insertion, MBist generation insertion and Boundary scan implementation at fullchip level
- DFT RTL coding and integration. DFT DRC/Linting checks. Create DFT modes timing constraints
- Implement & Debug iJTAG and IEEE 1149/1500 core wrapper-based architecture
- SCAN and Logic-BIST insertion
- ATPG - Pattern Generation, Verification at fullchip level & Pattern Diagnosis & Debug ATE pattern failures.
- High Speed interface DFT management and Analog Test Strategy
- Support other SOC functions (FE Design, Physical Design) End and Test Engineers

You'll be working in an empowered environment with state of the art methodologies and tools, to contribute to STM32 worldwide success.
A multicultural environment and its diversity are the strength of our dynamic team. A structured development plan will evolve with you along all your career.
We are looking for people with enthusiasm, constantly curious and creative towards continuous innovation, with good communication skills.
Join & Grow with us!

Profile
Educational Qualification :
Bachelors/Masters in Electronics/Electrical Engineering

Technical Skills/Knowledge Requirements :
- Strong DFT Fundamentals
- End-to-end DFT execution capability & experience including silicon bring-up
- Good RTL (VHDL or Verilog) skills. SOC integration and RTL modification as per DFT requirement
- Working knowledge to use industry standard tools like Tetramax, Design Compiler, etc. Experience in follow-up/closure of tool issues with EDA CAD vendors
- Working Knowledge in RTL, Gate-level simulations and debug, including silicon-debug
- Working Knowledge of Boundary Scan Testing and testing of IPs viz ADC, FLASH , PMU in standalone mode.
- Expert in ATPG coverage analysis to achieve high test coverage at SoC level.
- Competence in DFT DRC/Linting/Spyglass checks
- Hands on experience with JTAG protocols, Scan and MBIST architectures and tools (SMS, MMB)
Education: Any Graduate
Industry: Telecom, IT-Hardware/Networking

Skills Required