Job Description

Minimum qualifications: Bachelor\'s degree in Electrical Engineering, Computer Science, or equivalent practical experience. 3 years of experience designing RTL digital logic using SystemVerilog for Field-programmable Gate Array (FPGA), ASICs, or equivalent practical experience. Experience with a scripting language such as Perl or Python. Experience in area, power, and performance optimization. Preferred qualifications: Master\'s degree or PhD in Electrical Engineering or Computer Science. 3 years of experience in a relevant field. Experience with ASIC design methodologies for clock domain checks and reset checks. Experience implementing Camera Image Signal Processor (ISP) image processing blocks or other multimedia IPs, such as Display or Video Codec. Experience in area, power, and performance design optimization. Proficient in scripting languages, C or C++ programming, and software design skills. About the job Our computational challenges are so unique we can\'t just purchase off-the-shelf hardware, we\'ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google\'s services. As a Hardware Engineer, you design and build the systems that are the heart of the world\'s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users. With your technical expertise, you lead projects in multiple areas of expertise (e.g., engineering domains or systems) within a data center facility, including construction and equipment installation, troubleshooting, or debugging with vendors. Google\'s mission is to organize the world\'s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people\'s lives better through technology. Responsibilities Provide the microarchitecture definition for the Camera IP hardware designs, and subsystem or ASIC top-level integration. Define and develop RTL implementations that meet competitive power, performance, and area targets. Perform RTL coding, function simulation debug, performance simulation debug, and Lint, CDC, FV, and UPF checks. Participate in synthesis, timing closure, power closure, FPGA bring-up, and Silicon bring-up. Participate in test plan and coverage analysis of the sub-system and chip-level verification.

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