Job Description

At Microchip, we work every day to innovate and develop products that solve our customers' technology challenges. Our team of more than 20,000 people worldwide is dedicated to delivering on the promise of working together to improve lives.

Learn about our
guiding values that are the building blocks and foundation of our culture and discover how we make a positive impact in the communities in which we operate. We believe our culture fosters trust, collaboration and belonging.

Our people serve the industrial, computing, automotive, communications, aerospace and defense, and consumer market segments. As part of our global team, you can build technology solutions in our six growth areas - 5G, data centers, autonomous driving, the Internet of Things, electric vehicles, and artificial intelligence and machine learning.

Around the world, we are committed every day to recruiting, retaining and promoting people in our diverse workforce. Your perspective, passion and ingenuity will contribute to achieving more as we fulfill our
mission as a leading provider of smart, connected and secure embedded control solutions.

Join our community of exceptional people doing incredible things.

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Layout Design Engineers at are responsible for circuit layouts development for analog, memory and high speed layouts. By employing the industry leading tools, state of the art methodology, and innovative semiconductor cutting-edge technologies ranging from 16nm and below, the layout design engineer is responsible of the floor planning, physical design and verifications.

Requirements/Qualifications:

Requirements:
BE, B.Tech and above with minimum 6+ years of experience in layouts. Good understanding of advanced semiconductor technology process and device physics. Hands on experience in doing layout of High Speed Interface circuits like LVDS, HDMI, Display Port; PLLs, CDRs; ADCs, DACs; Regulators etc. Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM, etc). Experience working on FINFET technology down to 16nm & below. Experience with floor planning, matching, balancing and DFM issues. Experience using Cadence tools including PEX netlist generation. Experiences with EMIR analysis, ESD, antenna and related layout solutions is preferable & Experience working on High Speed Layout Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.

Travel Time: