Rtl Design Engineer
Job Description
Must have hands on designed/implemented/Integrated DDR controller or DDR Phy design for a project(ASIC or FPGA).
Should be excellent in DDR protocol knowledge.
Must be an expert in micro architecture and RTL coding.
Skill set needed Verilog, SoC & Sub-system RTL Integration, knowledge of industry known standards Interfaces (AXI, AMBA, NOC, Fabric, UCIE, PCIE, SATA, DDR etc. etc.)
Scripting (Shell, python, ruby, perl etc.), CDC & LINT Checkers, Synthesis, LEC, Constraints/SDC understanding, Clocking, UPF, Register roll up.
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Job Detail
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Job IdJD3257186
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IndustryNot mentioned
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Total Positions1
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Job Type:Full Time
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Salary:Not mentioned
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Employment StatusPermanent
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Job LocationBangalore, Karnataka, India
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EducationNot mentioned
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ExperienceYear