PV
Location: Bangalore
:
Will be responsible for Runing Physical verification analysis for multiple designs, analyzing results and providing fixes to address the issues for complex cpu designs, in latest technology nodes.
n (LVS, DRC, ERC, PERC, Antenna, DFM) at block and top levels. Collaborate with Physical Design (PD), RTL, and CAD teams to resolve PV issues and ensure sign-off quality.
Analyze and debug PV violations using Calibre tool and provide fixes to be taken using PnR tools like Innovus Understanding of all Physical verification signoff checks
Understanding of DRC/LVS/ANTENNA for latest technology nodes and solving the issues Basic Scripting in TCL/SHELL/...
Good communication skill for explaining issues/solutions Good skill for working with team.
Experience (years) : 3+ years
Education Qualification:
BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent
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