Company Description
At Western Digital, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible.
At our core, Western Digital is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we've been doing just that. Our technology helped people put a man on the moon.
We are a key partner to some of the largest and highest growth organizations in the world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world's biggest companies and public cloud, Western Digital is fueling a brighter, smarter future.
Binge-watch any shows, use social media or shop online lately? You'll find Western Digital supporting the storage infrastructure behind many of these platforms. And, that flash memory card that captures and preserves your most precious moments? That's us, too.
We offer an expansive portfolio of technologies, storage devices and platforms for business and consumers alike. Our data-centric solutions are comprised of the Western Digital, G-Technology(TM), SanDisk and WD brands.
Today's exceptional challenges require your unique skills. It's You & Western Digital. Together, we're the next BIG thing in data.
In this position, the individual will be responsible for implementing Place-And-Route for Low Power Designs from netlist to GDS. Responsibilities will include complete ownership of sub chip/Top Level PnR environment, clock tree design and driving Place-And-Route flow for full chip convergence and timing closer.
This position requires a Master's Degree in Electrical Engineering or Computer Science with a minimum of 6 to 10 years of hands on experience in sub chip Place-And-Route flow with emphasis on 7nm and low power designs. Proficiency in Innovus / ICC II / Prime Time and experience in PERL/TCL/Shell scripting is a must.
The individual must have hands on experience with multiple low power hierarchical and flat ASICs at 7nm and below nodes. Having exposure to Physical Verification flow for DRC and LVS closure for blocks is preferred. Ability to work with minimal supervision and drive to exceed expectations is a must. Good verbal and written communication skills are required.
Qualifications
The candidate must have:
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