Job Description

This job opening is for a platform Signal and Power integrity analysis engineer in a team responsible for high-complex platform design in AMD s microprocessor designs. With a good mix of experienced designers and recent college graduates from top Engineering institutions across the country, this team offers a very competitive atmosphere with excellent scope to learn and improve. Meticulous execution routine resulting in a solid track record, a strong focus on innovation and a balanced work-life distribution makes this one of the top-class teams in this space across the industry. THE PERSON: Ideal candidate would be the one with not only strong Signal and power integrity analysis knowledge, but also clear communication and presentation skills along with diligent documentation of work. Passion to go beyond the call of duty and innovate for higher efficiency would be a key differentiator. KEY RESPONSIBILITIES: Complete ownership of signal and power integrity issues of high-speed serial interfaces. Experience working with the actual product package/board design and analysis, SI/PI methodology development, and lab correlation/validation of the simulation results. Responsible for layout constraints preparation, layout review for signal and power integrity guidelines. Interface with cross-functional teams like Layout, FW, Mechanical Thermal. PREFERRED EXPERIENCE: Experience with Cadence Sigrity design suit, Ansys SI wave/HFSS, Keysight ADS. Possess strong fundamentals in 3D/2D EM simulation tools and transmission line theory Expertise in DDRx memory bus designs preferably using Mentor HyperLynx or Cadence Sigrity SI suit. Expertise in the design of serial links including NRZ, multilevel signaling (PAM4), COM, jitter analysis and SERDES equalization techniques with CTLE, DFE and FFE is required. Expertise in channel model construction of serial links cascading s-parameter data of PCB, connector, and cable to generate a complete system model for an end-to-end simulation. At the minimum working level knowledge with Cadence Allegro design layout tool, its constraint manager, and schematics. A high-level knowledge about behavioral device modeling including IBIS and IBIS-AMI models as well as passive device modeling techniques with touchstone files. A high-level knowledge about SI and PCB design fundamentals including single ended and differential signals, signal loss, impedance control and crosstalk noise is required. Experience in the simulation of parallel interfaces including FPGAs, SDRAMs, Flash memory devices. A good grasp of fundamentals circuit and electromagnetics theory including frequency and time domain analysis techniques, transmission line theory, termination techniques, generating and interpreting data-eye diagrams, bathtub curves with NRZ and PAM4 signaling techniques. A working knowledge of PCB stack-up design with fabrication limitations and cost trade-offs along with experience of high frequency PCB material. Significant SI lab experience with TDR and VNA measurements. Maintain standards compliance Anticipate, identify, and solve problems independently Be self-motivated and willing and able to operate with little direct guidance or supervision, work effectively with incomplete or un-defined requirements. Basic platform Board bring-up testing. Layout review and co-ordination with cross functional teams Interaction with cross functional teams ACADEMIC CREDENTIALS: B.E/B.Tech (EEE, ECE)

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