Job Description

Packaging R and D Engineer is responsible for defining and developing Assembly Test Chips used to certify new Intel processes. -Responsible for leading the definition and development of Assembly Test Chips/Design Rules used to certify next gen package concepts and architectures and for IFS customers. -Owns definition and design of Full loop Assembly Test chips used to understand chip-package interactions for package technologies. As part of this job role, the candidate will be required to work with other partners within ATTD/Fab/Foundry to define test chip floorplans and coordinate layout. -Provides design solutions in test chips for ESD protections, incorporating basic IP blocks, generating DR compliant layouts on full metal stacks -The candidate should also exhibit the following behavioral traits: Proven team player with demonstrated collaboration with customers; Willingness to work independently with good listening, written and verbal communication/presentation skills

Qualifications

Minimum Qualifications: 1. Familiarity with Cadence Virtuoso suite of tools 2. Possess a Masters in electrical, mechanical, material science or related field 3. Familiarity with assembly processes, chip package interaction 4. Experience with DRC/DFM for Intel 16 process node and beyond 5. Experience with full chip integration and device tape-in using Cadence Virtuoso. Preferred Qualifications - Experience with other Si EDA platforms such as Synopsys ICC/ICWorkbench is a plus

Inside this Business Group

As the world\'s largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art - from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore\xe2\x80\x99s Law to bring smart, connected devices to every person on Earth.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel\xe2\x80\x99s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
JobType Hybrid