Job Description

Company: Qualcomm India Private Limited

Job Area: Engineering Group, Engineering Group
Hardware Engineering

General Summary:

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. As a DV Engineer with a focus on SoC DFD (Design for Debug) verification, you will work to understand the internal requirements and complexities of our highly complex data server SOC and architect the required verification strategy. You will help set up methodologies, develop test plans, and verify that the design meets the highest quality standards. We believe in early involvement of DV, so you will also participate in architecture/product definition through early involvement in the product life-cycle.

Minimum Qualifications: . BA/BS degree in Electrical Engineering with 4+ years of practical experience

• Strong fundamentals in digital ASIC verification
• Knowledge of SOC Debug architecture
• Experience in verification of SoC debug infrastructure, Debug security, ARM Coresight architecture, Traces/Triggers use cases and other debug techniques such as ScanDump Verification
• GLS verification experience
• Familiarity with system level HW and SW Debug techniques and Verification requirements

Preferred qualifications

• MS degree in Electrical Engineering; 4+ years of practical experience
• Expertise in the verification of IP/SS/System level debug architecture, including System level traces, triggers infrastructure, debug security
• Familiarity with ARM coresight and/or other custom SoC debug architecture
• Exposure to ARM Core debugging techniques using external debugger such as ARM-DS/Lauterbach would be a plus
• Experience in DFx DV techniques such as ScanDump, JTAG TAP/iJTAG chain understanding would be a plus
• Strong understanding of AMBA, JTAG bus protocols
• A good understanding of the complete verification life cycle (test plan, testbench through coverage closure)
• Extensive knowledge in multiple testbench structures
• Exposure to FPGA and emulation platform debugs
• Proficiency in UVM, C/C++
• Experience w/ PSS or higher-level test construction languages
• Knowledge of assertion-based formal verification is an added advantage

Roles and Responsibilities

• Define entire verification architecture for all security verification at unit , SS and System level
• Define verification architecture, develop test plans and build verification environment
• Work with design team to understand design intent and bring up verification plans and schedules
• Verify Subsystems and Full SoC using advanced verification methodologies
• Build agents and checkers from scratch. Perform and write test plan from design architecture specs and/or protocol standard
• Debug test cases and report verification result to achieve expected code/functional coverage goal
• Assist in emulation, FPGA, prototyping efforts
• Assist in silicon bring-up, debug and characterization

Applicants: If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email to

Although this role has some expected minor physical activity, this should not deter otherwise qualified applicants from applying. If you are an individual with a physical or mental disability and need an accommodation during the application/hiring process, please call Qualcomm's toll-free number found for assistance. Qualcomm will provide reasonable accommodations, upon request, to support individuals with disabilities as part of our ongoing efforts to create an accessible workplace.

Qualcomm is an equal opportunity employer and supports workforce diversity.

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If you would like more information about this role, please contact .