Job Description

40512BR
INDIA - Noida
and Requirements
Position Summary:

Responsible for managing the embedded memory Layout Development functions- which includes spec definition, layout design, development, troubleshooting, debugging, verification and formal release of memory layout/compilers

Responsibilities & Duties:
Below are the key roles and responsibility of the candidates:

• Technology analysis- specially on lower nodes like 5nm or below for the development of a competitive product.
• Experience in providing architectural solutions to achieve required performance (area, power and delay).
• Defining the specifications/guidelines for a particular node for helping the team at platform level.
• Enablement of tools for catering to specific requirements for a platform, which may include continuous alignment with Foundry/CAD team.
• Understand the existing off the shelf memory product so as to propose innovative solution catering to dynamic business requirements.
• Provide memory IP solution roadmap to cater to the future demand.
• Driving the Layout Development activity for SRAM/ROM embedded memories with optimum quality.
• Tracking of commitments for both internal and external shipments.
• Troubleshooting of key items like complex DRC/Antenna/ESD rules along with EM and IR setups and corresponding debugging of results.
• Enablement of QA flows with zero bug completion approach.
• Managing technically sound memory layout team.
• Last but not the least, on time escalation of any burning item on quality side.

Qualification:

• Diploma in EE with 12+ years of relevant experience on SRAM/ROM with exposure on lower nodes
• BE in EE with 10+ years of relevant experience on SRAM/ROM with exposure on lower nodes
• MS with 8+ years of relevant experience on SRAM/ROM with exposure on lower nodes

Skills:

#Required

• Strong knowledge of physical verification: DRC, LVS, ANT, ERC, EM-IR, DFM,DENSITY,IP INTEGRATION CHALLENGES, Extractions etc.
• Deep understanding of various embedded memory architecture: low power, high density, low standby power, high speed, synchronous/asynchronous architecture and various combination of such figure of merits.
• Strong understanding of memory layout techniques: dense designs, regular style, DFM compliant layout, matching (local and global), shielding, etc.
• Life time effect know how (EM, IR drop, Self-heating, HC, NBTI, PBTI, etc.)
• Prompt response to customer queries
• Skillset to generate ideas towards productivity improvement and quality optimization.
• Ability to think out of the box for bringing automation into our day to day activities.
• Quick learner to adapt Synopsys flows

#Desired

• Excellent communication skills
• Good analytical skills
• Ability to take initiative.
• Adaptability and flexibility as per business requirements.
• Team player, eager to learn, engage curiosity, develop deep competency.

About Synopsys:

At Synopsys, we are at the heart of innovations that change the way we work and play. Self-Driving cars, Artificial Intelligence, The cloud, 5G, IOT. We are powering all listed items with world’s most advanced technologies for chip design and security software. If you share our passion of innovation, we want to meet you
Disclaimer:
Synopsys considers all applicants for employment regardless of their gender, race, colour, religion, geography, sexual orientation, age, gender identity.
Job Category
Engineering
Country
India
Job Subcategory
Layout Design
Hire Type
Employee