Job Description

IO Layout


Location: Bangalore


:


Very Good Knowledge on GPIO layouts and performing Layout verifications. Good Exposure to Technologies of GF 55nm , UMC 55nm , TSMC 28nm, TSMC 12nm etc. Should have Solid experience in Layout design and Verifications of all the blocks of a GPIO library like Driver, predriver, receiver, ESD clamps. Should be in position to technically drive the Layout Implementation starting with floorplanning, placement , IO ring Implementation , IO Bus design . Very good hands on knowledge on the Cadence Virtuoso layout verification suite relevant to the above mentioned technologies. Very good understanding of ESD & LU concepts and corresponding Layout Implementation strategies and challenges. Working (hands on) knowledge of Linux OS and Unix Shell & PERL scripting will be a plus. Good team player in a multi-site work environment Working knowledge with load sharing systems like LSF will be a plus. Very Good Knowledge on GPIO layouts and performing Layout verifications. Good Exposure to Technologies of GF 55nm , UMC 55nm , TSMC 28nm, TSMC 12nm etc. Should have Solid experience in Layout design and Verifications of all the blocks of a GPIO library like Driver, predriver, receiver, ESD clamps. Should be in position to technically drive the Layout Implementation starting with floorplanning, placement , IO ring Implementation , IO Bus design . Very good hands on knowledge on the Cadence Virtuoso layout verification suite relevant to the above mentioned technologies. Very good understanding of ESD & LU concepts and corresponding Layout Implementation strategies and challenges. Working (hands on) knowledge of Linux OS and Unix Shell & PERL scripting will be a plus. Good team player in a multi-site work environment Working knowledge with load sharing systems like LSF will be a plus.

Experience (years) : 4-9 years


Education Qualification:


BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent