FPGA
Location: Hyderabad
:
Exp on Video domain IPs / Digital IPs.
Exp of one or more of protocols at the IP level: MIPI CSI / MIPI DSI / DisplayPort /HDMI / SDI.
Job Requirement:
Hands on experience with architecting / micro-architecture.
Verilog/ System Verilog RTL coding for FPGA designs.
Lint, CDC, synthesis flow and static timing flows, formal checking, etc. experience.
Experience (years) : 7-12 yrs
Education Qualification:
BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent
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