FPGA
Location: Hyderabad
:
Responsibilities include packing RTL files into IP using AMD packaging methodology
Excellent TCL and PERL/Python concepts and experience in Verilog / System Verilog design and verification.
Working knowledge of UNIX environment desired.
Job Requirement:
Expertise with FPGA architecture and Xilinx-AMD, Vivado
Debug skills using tools like VCS, xcelium and Questa.
Experience (years) : 3-6 years
Education Qualification:
BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent
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