DV(DFT)
Location: Bangalore
:
Develop testbench using System Verilog/UVM based on test plan
Run full-chip level DFT tests with both RTL and netlist
Debug any simulation failures
Familiarity with System Verilog/VCS/Verdi/DVE
Familiarity with JTAG/P1500
Scripting skills: Python/Perl
Knowledge about UVM
Knowledge about ATPG concepts
Experience (years) : 5+ years
Education Qualification:
BE/ME
MNCJobsIndia.com will not be responsible for any payment made to a third-party. All Terms of Use are applicable.