8+yrs
The role involves verification of power management features at the SoC level, focusing on ensuring functional correctness and robustness of power gating (PG) and other low-power mechanisms.
The candidate will be responsible for power-aware verification using UPF (Unified Power Format), validating power domains, isolation strategies, retention, and sequencing across the SoC.
Hands-on expertise in C, C++, SystemVerilog (SV), and UVM is required to develop and enhance testbench components, create power-aware test scenarios, and debug complex SoC-level interactions. The position demands a strong understanding of SoC power architecture, low-power design concepts, and verification methodologies to ensure comprehensive coverage and high-quality silicon results
MNCJobsIndia.com will not be responsible for any payment made to a third-party. All Terms of Use are applicable.