Company DescriptionRenesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world\xe2\x80\x99s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what\xe2\x80\x99s next in electronics and the world.LOCATION : NOIDADesign for Test (DFT) engineering organization at Renesas Electronics works on groundbreaking methods & technologies for innovations in the area of DFT architecture, verification & post silicon bring up of state-of-the-art semiconductor chips like system on a chip (SOCs) built on the latest semiconductor technology nodes.Responsibilities:
You will lead the DFT team activities at your location to drive the DFT structures implementation on the complex SOCs, verify the DFT operations of the chips & support the silicon bring up team using the DFT vectors on the ATE machines. Your team will own the following activities.
1. MBIST insertion to the design.
2. Compressor based Scan chain insertion.
3. BSCAN structure insertion based on the IEEE 1149.1 & 1149.6 standards.
4. Logic BIST implementation for the Self-test capability
5. Analog BIST implementation for selected analog blocks like PLLs, ADC & DACs.
6. IOBist methods implementation for IO structures of the SOCs.You will lead your team to work with cross-functional teams like design, physical design, verification teams to deliver the DFT solutions to the SOCs in predefined schedule.Qualifications
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