Dft Engineer
Year Bangalore, Karnataka, India
Job Description
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- Will be responsible for Designing and Implementing DFT techniques
- Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability.
- Test Modes implementation and verification, scan insertion including on-chip compression.
- Implementing, integrating and verifying memory BIST and boundary scan .
- ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test Coverage and simulations at gate level with timing (SDF).
- Basic understanding of complete SOC design and flow.
- Excellent in problem solving and analytical skills
- Excellent communication, team work and networking skills
- Should Have Good understanding of Design and DFT Architecture
- Should have been part of Tapeout SoC
- Well Versed with ATPG Tools & MBIST Tools
- Team Player, Strong Business Acumen with understanding of organizational issues (conflict resolution between stakeholders)
- Familiarity with Desired Flexibility and adaptability with respect to project management
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Job Detail
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Job IdJD2956034
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IndustryNot mentioned
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Total Positions1
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Job Type:Full Time
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Salary:Not mentioned
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Employment StatusPermanent
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Job LocationBangalore, Karnataka, India
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EducationNot mentioned
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ExperienceYear