Job Description

Overview:
TekWissen Group is a workforce management provider throughout India and many other countries in the world. The below client represents the connected world, offering innovative and customer-centric information technology experiences
Position: Design Flow Engineer - I - RTL
Location: Noida
Duration: Full Time
:

• We need more than 7 year experience candidate with following criteria
• Expertise and hands on experience in Verilog/RTL design for IP or SoC.
• Command and thorough knowledge on digital logic design concepts.
• Must have worked on at least one large IP block and have in depth knowledge of IP block design/architecture.
• Must have experience in Synopsys/Cadence/Mentor simulation tools and debugging skills.
• Desirable Perl/TCL scripting and automation knowledge
• Desirable experience in RTL logic synthesis, sdc and constraint writing experience
• Understanding of basic soc architecture std-cells, IO blocks etc.

TekWissen Group is an equal opportunity employer supporting workforce diversity