Asic/layout Design Engr, Sr I

Year    Noida, Uttar Pradesh, India

Job Description



40559BR
INDIA - Noida
and Requirements

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules. We’re looking for a Senior Analog Design Engineer to join the team.Does this sound like a good role for you? This role involves analyzing various mixed signal techniques for dynamic and static power reduction, performance enhancement and area reduction. You’d leverage your strong understanding of circuit simulation and circuit layout as well as knowledge of bipolar, CMOS, passive structure, and interconnect failure modes. You will be part of a strong development team in the area of High Speed PHYSICAL Interface Development. You will develop Analog Full custom circuit macros, i.e., PLL, Regulators, equalizers, Analog Front End, needed for High Speed PHY IP, in planer and fin-fet CMOS technology.. You will be working with experienced teams locally and with people from various sites spread across the globe.Key Qualifications

  • BE with 3 -10 years of relevant experience / MTech 2-10 years of relevant experience in Electrical/Electronics/VLSI Engineering or other relevant field of study.
Mandatory Experience
  • CMOS circuit design fundamentals, device physics, basic understanding of layout and parasitic extraction, spice simulation, sub-micron design methodologies, PLL/DLL, Voltage Regulators, data converters, Equalizers, Impedance calibrators.
  • Hands ON experience with spice simulations and various sub-micron design methodologies.
  • Analog transistor level circuit design in nanometer technologies.
  • Experience in Multi Gbps range High speed designs.
  • Can micro architect circuit from specifications, can create simulation benches to verify the specification, can understand and debug circuit.
  • Should have understanding of layout and parasitic extraction.


Preferred Experience
  • Experience in Multi Gbps range High speed analog transceiver designs
  • Experience in design of Analog front-end transceivers, PLLs, Regulators, Bandgaps, Equalizers (CTLE, FFE, DFE), Impedance calibrators, serializer , Deserialisers etc.
  • Familiarity with automation / Scripting language.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Job Category
Engineering
Country
India
Job Subcategory
Layout Design
Hire Type
Employee

Beware of fraud agents! do not pay money to get a job

MNCJobsIndia.com will not be responsible for any payment made to a third-party. All Terms of Use are applicable.


Related Jobs

Job Detail

  • Job Id
    JD2883774
  • Industry
    Not mentioned
  • Total Positions
    1
  • Job Type:
    Full Time
  • Salary:
    Not mentioned
  • Employment Status
    Permanent
  • Job Location
    Noida, Uttar Pradesh, India
  • Education
    Not mentioned
  • Experience
    Year