Job Description

At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're pow

At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world's broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and requirements of their target applications. And get differentiated products to market quickly with reduced risk. Staff Digital Verification Engineer The Digital Design Engineer, Staff works on PHY IP verification related to complex protocols. The position offers excellent learning and growth opportunities. This is a technical lead role offering a challenging career path. The role involves developing and working on design of high speed PHYs and Serdes. Additionally you will be involved in: . Design architecture development and its review . RTL design development . Debug of simulations, including those of real signals modeled using SV for analog . RTL, GLS, Co-simulations . Deliver high quality RTL and other simulation models to customer . Participate in technical reviews and contribute actively . Participate in customer support with bring-up of IP in customer simulation environment . Participate in review of SERDES / PHY / Controller IP specification to validate compliance to protocol of interest . Follow and improve development process ensuring high quality output Candidate should be B.E./B.Tech or M.E./M.Tech in Electronics/Telecommunication/Computers as major subjects, plus a minimum of 8 years of digital design and verification experience in the industry. Skill Set . Hands on experience with HVL, or HDL like VHDL, System Verilog . Knowledge of Perl/Shell scripts . Knowledge of protocols like Ethernet, PCIe, other networking protocols . The candidate should have good communication skills, be a team player with leadership qualities, good problem solving and interpersonal skills. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.