Job Description

and Requirements

The candidate will be part of the R&D in Solutions Group at our Bangalore/Pune Design Centre, India. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers opportunity to work in a multi-site environment on IP Design of complex cores using latest HDL and design flows .

The candidate will be part of the DesignWare IP Design R&D team at Synopsys.
He / She will be expected to specify, design/architect and implement state-of-the-art RTL designs for the DesignWare family of synthesizable cores.
He/ She will work closely with other RTL designers and be part of a global team of expert design engineers.
Will be working on the next generation connectivity protocols for commercial, Enterprise and Automotive applications

Job Responsibilities -

• Will be working on the next generation High Performance connectivity protocols for commercial, Enterprise and Automotive applications
• Understand Standard Specifications/ functional specifications/ feature enhancements for the product and create architecture, micro-architecture with detailed design documents for some of the components of the design for medium to high complexity functionality.
• Be an individual contributor in Design Tasks - RTL coding of design, synthesis, CDC analysis, debug, test development etc.
• May need to interact with customers to discuss/ understand customers\' specification requirements, if needed .
• The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide.

Must have BSEE in EE with 8+ years of relevant experience or MSEE with 7+ years of relevant experience in the following areas:

• - Knowledge of one or more of protocols: MIPI-I3C/UFS/Unipro, AMBA (AMBA2, AXI) is highly desirable, exposure to others protocols such as SD/eMMC, Ethernet, DDR, PCIe, USB is a plus

• Hands on experience with architecting/ micro-architecture/ detailed design from functional specifications. Must have worked on control path oriented designs like asynchronous FIFO, DMA architectures, SPRAM/ DPRAM interface design, etc.
• Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for ASIC designs and simulation tools
• Lint, CDC, Synthesis flow and static timing flows, Formal checking, etc. is a must for candidates with design background.

• Experience with Scatter Gather DMA design. Host controller interface is a significant plus.

• Experience with Perforce or similar revision control environment
• Knowledge of Perl/Shell scripts.
• Exposure to quality processes in the context of IP design and verification is an added advantage
• Exposure to Formal verification is a definite plus.
• Ability to work/ prior experience as a technical lead for a small team is a major plus.
• In addition, the candidate should have good communication skills, should be a team player and possess good problem solving skills and show high levels of initiative.

This position requires prior industry experience and is not open for college fresh grads.

Location: Bangalore/Pune

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Hire Type

Employee

Job Category

Engineering

Job Subcategory

ASIC Digital Design

Synopsys