Job Description

and Requirements

VC Formal AE team is looking for motivated, self-starter and talented applicants to join our growing and thriving team in India. The position is technically challenging and holds great responsibilities. In return, there is an exceptional career growth path for applicants who excel in the fast moving and high rewarding environment. The candidate will be part of an agile global team that works very closely with top customers and ensures the high quality of our solutions in a constantly changing and highly results oriented environment. The ideal candidate will be self-starter, will thrive in a fast-moving setting, is hungry for understanding and is motivated to grow and take on more responsibilities in the organization. The applicant will have the opportunity to learn a multitude of hardware and software tools, new hardware and software languages, and be exposed to the latest development in the industry.

The candidate will perform product validation tasks such as examining requirements, designing RTL blocks, developing formal environments, running a multitude of EDA tools, and developing scripts for automation. Will work closely with R&D, global CAEs and customers to specify and develop next generation features, capabilities and applications. Includes examining of the environment and setup, identification of appropriate blocks and metrics, examination of root-cause of tool performance and problem complexity, and optimizing modeling, formal test benches and environment for optimal tool performance. Ensures that client\'s needs have been met and that the product/solution is fully functioning according to specification. Application of formal verification including formal property verification, sequential equivalence checking, formal coverage, connectivity checking and other formal verification apps.

Location: Bangalore/Noida India

Requirements and Desirable Skills:

• EE graduate from reputed school. Post-graduates are preferred

5-7 yrs. of industry experience in RTL design or verification engineers involved in deploying verification methodology using simulation-based technologies * Exposure to assertion-based verification (in simulation) is preferred and experience with formal verification tool is desirable but not mandatory

• Managing verification responsibility for hardware designs, verification consulting experience is desirable
• Good understanding of hardware design (Verilog/VHDL) and micro-architecture.
• Exceptional understanding of Unix/Linux automation shell (bash, csh) and scripting (Tcl, Perl, Python)
• Great oral and written communication skills.
• Ability to work autonomously

Hire Type

Employee

Job Category

Engineering

Job Subcategory

Applications Engineering

Synopsys