Analog Layout
Location: Bangalore / Hyderabad
:
TSMC 16/12nm,7nm,5nm,3nm and below (other foundries are also fine like Intel, Samsung, GF). Preferably TSMC 5nm/3nm experience.
Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.
Verification flows - LVS/DRC/DFM/Antenna check/EMIR experience.
Responsible for on-time delivery of block-level layouts of acceptable quality.
Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must.
BE or MTech in Electronics/VLSI Engineering
Good communications skills as we work with cross-functional teams.
Share the profiles who have good hands-on experience in recent times on lowers nodes.
TM should work independently.
4 to 8 years of experience - flexible
If a candidate has HBM experience, it is an added advantage. Analog blocks like Regulators/Charge pumps/Power Management etc..
Job Requirement:
TSMC 2nm or 3 nm
Experience (years) : 4-8 years
Education Qualification:
BTech
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