To develop advanced Mixed Signal IP designs which includes Clock Generation IPs PLL and Oscillators and other mixed architectures. Ability to work on work on low power specialized designs in differentiated sub-micron technologies.
Major responsibilities include. Discussing with the Divisional customer and end customer and finalizing the specifications
Handling the Design reviews with the Customer, discussions, preparation, technical driving , sync with the various activities of the division , driving designers, layout designers , packaging , ESD, system level constraints, package constraints and board level constraints to get the optimized and timely solution
Profile
Developing IP solutions suitable for customer needs Driving innovation and develop new architectures for best-in-class solution Driving new IP development to add value in SOCs
Coaching and mentoring junior design engineers
Position location
Job location
Asia-Pacific, India, Greater Noida Candidate criteria
Education level required
4 - Bachelor degree
Experience level required
6-10 years
Languages
English (2- Business fluent) Requester
Desired start date
01/12/2023
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