In this role you would have the following responsibilities : Ensure analog sub-block performance adheres to SerDes standards and architecture document specifications Identify and refine circuit implementations to achieve optimal power, area and performance targets Propose design and verification strategies that efficiently use simulator features to ensure highest quality design Oversee physical layout to minimize the effect of parasitics, device stress, and process variation Present simulation data for peer review Ownership of analog and mixed-signal building block that is integrated as part of a larger SerDes design Document design features and test plans Consult on the electrical characterization of your circuit within the SerDes IP product Key Qualifications: PhD with 3+ years, or MTech/ MS with 5+ years of SerDes/High-Speed analog design experience Familiarity with transistor level circuit design of fundamental analog and mixed -signal building blocks - sound CMOS design fundamentals Silicon-proven experience implementing circuits for analog and mixed-signal building blocks Design experience with some of the following SerDes sub-circuits: receive equalizers, data samplers, voltage/current-mode drivers, serializers, LDOs, Bandgap, ADC/DAC, PLLs, DLLs
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