Job Description

VLSI: Constraints writer / Constraints management

Key Responsibilities

Develop, manage, and maintain

design constraints

for complex SoC/IP designs. Work with

TIM Vision or Galaxy Constraints tools

to generate, validate, and optimize constraints. Perform

Check Design

and

Check Timing

to ensure constraints meet design and timing requirements. Review timing reports, identify violations, and apply correct

timing exceptions

(false paths, multicycle paths, case analysis). Collaborate with RTL design, physical design, and STA teams to ensure clean handoff and closure. Debug constraint issues and improve constraint quality across design stages. Ensure constraints are consistent across different design hierarchies and flows.

Technical Skills Required

Strong understanding of

timing constraints

(SDC). Experience in

TIM Vision

or

Galaxy Constraints flow/tools

. Knowledge of STA concepts (setup/hold, clock definitions, generated clocks, I/O delays). Ability to identify and apply

timing exceptions

safely and correctly. Hands-on experience with

Synopsys

or

Cadence

timing tools (PrimeTime, Tempus preferred). Good understanding of digital design fundamentals and RTL-to-GDS flow. Scripting knowledge (Python / TCL / Shell) for automation is a plus.

Soft Skills

Strong analytical and debugging skills. Ability to work with cross-functional teams. Good communication and documentation skills.
Job Type: Full-time

Pay: ₹363,997.72 - ₹2,069,241.25 per year

Work Location: In person