Job role: Develop State-of-the art design methodology to enable Foundation IPs for SoC development. Develop and validate EDA Views for Standard-Cell and IO libraries in 28/16/5nm technology nodes. Interface with PDK, Foundation IP and other methodology teams to understand library/cell architecture, design flow requirements and device methods for EDA view generation and validation. Architect and develop/support validation checks and automation methods for productivity improvement. Explore and implement AI/ML methods for enhancing accuracy of models and Design throughput.Required Skillset:
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