Verification Engineer

Year Bengaluru, Karnataka, India

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Job descriptionResponsibilities:

You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites.
Architect and Develop block level verification environments for sub-system and fullchip using System Verilog and UVM methodology.
Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems. Use various front-end simulator tools (VCS/NC) to perform this activity.
Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage and Gate level simulation.
Develop Perl, Python and/or shell scripts to improve current verification infrastructure/methodology

Required Skills:

Job Type: Full-timeSalary: From ?1,300,000.00 per yearSchedule:

Ability to commute/relocate:

SJR, I-PRAK, Bangalore, Karnataka: Reliably commute or planning to relocate before starting work (Required)

Experience:

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