Job Description

Rockwell Automation is a global technology leader focused on helping the world\xe2\x80\x99s manufacturers be more productive, sustainable, and agile. With more than 25,000 employees who make the world better every day, we know we have something special. Behind our customers - amazing companies that help feed the world, provide life-saving medicine on a global scale, and focus on clean water and green mobility - our people are energized problem solvers that take pride in how the work we do changes the world for the better. We welcome all makers, forward thinkers, and problem solvers who are looking for a place to do their best work. And if that\xe2\x80\x99s you we would love to have you join us! The Engineer will be part of an ASIC/FPGA design team responsible for digital logic design of next generation and legacy products. The candidate will participate in modeling, RTL implementation, conversions and verification. The candidate should be familiar with C, C++, System Verilog and Verilog and/or VHDL. Must be able to work with supervision from more experienced engineers and engage in technical dialogue. The candidate should be familiar with ASIC/FPGA verification methodology to be able to create a Verilog/VHDL module test specification from the ASIC/FPGA functional specification and/or module specification created by the chip Architect or ASIC/FPGA Design Engineer. The test specification will include tests needed for the input/outputs, algorithms, state machines, clocks and other design details. The candidate will then implement the tests in VHDL/Verilog/System Verilog languages. The test code will then be verified in simulation and include coverage analysis of the tests. The candidate should be able to demonstrate the knowledge of ASIC/FPGA test methodology. Knowledge of the System Verilog\xe2\x80\x99s Universal Verification Methodology (UVM) is preferred. ESSENTIAL FUNCTIONS:

• Basic understanding of Digital Design fundamentals
• Knowledge of all phases of ASIC design and test methodology
• Expertise in Verilog / VHDL and System Verilog
• Experience in developing Verification Environment
• Experience in Unit Level and Top Level Verification
• Experience in developing BFM\xe2\x80\x99s and VIP\xe2\x80\x99s
• Proficiency in Test plan development
• Proficiency with industry standard simulators
• Scripting Skills \xe2\x80\x93 Shell, TCL, etc
• Linux/Unix environment
• Team Player
• Good Communication Skills

• Knowledge of Bus Protocols like AXI, AHB, SPI etc. and Ethernet Protocol
• Knowledge of System Verilog
• Knowledge of UVM
• Test Planning & Verification
• Knowledge of safety standards desirable
• Working Knowledge of various tools
  • Cadence: Incisive
  • Synopsys \xe2\x80\x93 VCS
• Formal Verification
• Proficiency in ARM Architecture
• Gate Level Simulation experience
• Low Power Simulation experience
• Dynamic CDC experience

• A BE / MS or ME / MTech / MS in an Electronics / Electrical Engineering discipline.
• Minimum of 3 years\xe2\x80\x99 experience with standard cell ASIC and / FPGA design.
• Candidate should be familiar with RTL, gate level design and verification using VHDL and/or Verilog hardware description languages.
• Demonstrated ability designing independently for medium/high complexity problems.
• Strong oral and written communication skills in English and ability to present technical information.