Job Description

Company Description

Western Digital Corporation is the world's largest data storage company with a leading portfolio of HGST, SanDisk, G-Technology and WD brands covering flash and disk-based solutions. Deployed by the largest and most prominent organizations worldwide, Western Digital solutions are everywhere, touching lives and enabling great value from the data they possess.

Innovating at the Boundaries of Technology:

Whether in your pocket, home, car, or the cloud, it's likely Western Digital is with you every step of the way. It's a responsibility we don't take lightly. That's why we are always at the cusp of innovation, pushing the boundaries of technology to make what you thought was once impossible, possible.

We deliver the possibilities of data. YOU define what's possible. The next big thing in data is you! Shape the future & define what's possible. Come shape the future with us. For more information about us, please visit us at



In this position, the individual will be responsible for providing technical leadership in the defining full chip Memory BIST and DFT methodology. Responsibilities will include complete ownership of full chip MBIST and DFT implementation flow, development, delivery and debug of test patterns. Additional responsibilities include proactively working with EDA vendors to assess best in class tools / capability and benchmark them to drive compelling adoption arguments. He / She will also drive IP integration strategies that ensure quality ASICs and avoid schedule surprises.

The individual will influence and shape Western Digital's next generation Design-for-Test implementation capability to meet the demands of the ASIC design road map. The individual will provide technical coaching and mentoring to junior team members and ensure the continued growth and success of the team. Ability to work with minimal supervision and drive to exceed expectations is a plus.

This position requires a Master's Degree in Electrical Engineering or Computer Science with a minimum of 10 to 14 years of direct experience in Memory BIST / DFT with emphasis on full chip ownership. Proficiency in Synopsys and MentorGraphics Test flows experience in PERL/TCL/Shell scripting is a must. The individual must have proven hands on experience leading the tape out of multiple low power hierarchical and flat ASICs at 65nm/40nm/28 nm designs. Expertise in DFT Compiler, Tetramax and Tessent is a MUST. Experience with synthesis is a plus. Good verbal and written communication skills are required.

Experience:

• 8-13 years

Must have:

• Experience in DFT architecture and implementation
• Experience in MBIST architecture and implementation

• Strong DFT/MBIST fundamentals

• DRC Clean up
• Coverage improvement
• Understanding and modifying MBIST algorithms
• Pattern validation flows

• Zero/Unit delay
• SDF based
• Diagnosis and Silicon Bring up flows

Good to have:

• PERL/TCL Scripting
• Usage of assertions for monitoring clock frequencies and other test related registers
• Yield analysis and improvement flow
• Understand CLP constructs and can work in multi-voltage, multi-power design

Expected Roles:

• Need to architect DFT based on the PETE, Design and Customer specifications
• Should be self motivated, self driven and eager to learn

Qualifications

B.E/B.Tech in Electronics Engineering. M. Tech is prefreable.

Additional Information

Because Western Digital thrives on the power of diversity and is committed to an inclusive environment where every individual can thrive through a sense of belonging, respect, and contribution, we are committed to giving every qualified applicant and employee an equal opportunity. Western Digital does not discriminate against any applicant or employee based on their protected class status and complies with all federal and state laws against discrimination, harassment, and retaliation, as well as the laws and regulations set forth in the "Equal Employment Opportunity is the Law" poster.