Job Description

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Role Proficiency:
Independently execute mid sized customer projects in any field of VLSI Frontend Backend or Analog design with minimal supervision
Outcomes: * Work as an individual contributor owning any one task of RTL Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.

• Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams
• On time quality delivery approved by the project manager and client
• Automate the design tasks flows and write scripts to generate reports
• Come up with novel ideas to reduce design cycle time and cost accepted by UST Manager and client

Measures of Outcomes: * Quality -verified using relevant metrics by UST Manager / Client Manager

• Timely delivery - verified using relevant metrics by UST Manager / Client Manager
• Reduction in cycle time cost using innovative approaches
• Number of papers published
• Number of patents filed
• Number of mandatory trainings attended adhering to training goals

Outputs Expected:
Quality of the deliverables: * Ensure zero bugs are present in the design / circuit design.

• Clean delivery of the design/module in-terms of ease in integration at the top level
• Meeting functional spec / design guidelines 100% without any deviation or limitation
• Documentation of tasks and work performed

Timely delivery: * Ensure project timelines as laid out by the client or program manager are met

• Meet intermediate tasks delivery for other team members to progress
• Calling out for help and support in the case of delay in tasks delivery

New Skills development: * Participate in training - skilling someone and also getting skilled in newer technologies

• Take up new areas of project development

learn on the job and deliver
Team Work: * Participation in team work and supporting team members at the time of need

• Able to take up additional tasks in-case of any team member(s) not available
• Able to hand hold junior team members to explain the project tasks and support to deliver
• Work dedication to go beyond the call of duty to ensure deadlines and quality are met

Innovation & Creativity: * Approach towards repeated work by automating tasks to save design cycle time

• Participation on technical discussion

training
forum
white paper etc
Skill Examples: * Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice

• EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (experience in one or more tools)
• Technical Knowledge:a. IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong Physical Design / Circuit Design / Analog Layout Knowledged. Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design
• Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below
• Strong communication skills and ability to interact with team members and clients equally
• Strong analytical reasoning and problem-solving skills with attention to details
• Ability to understand the standard specs and functional documents
• Ability to deliver the tasks on-time in a quality fashion per quality guidelines and GANTT
• Well versed with the available EDA tools and able to use them efficiently
• Required technical skills and prior design knowledge to execute the assigned tasks
• Ability to learn new skills in-case required technical skills are not present at a level needed to execute the project

Knowledge Examples:

• Knowledge of project(s) in any of the design by executing - RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.
• Understanding of the design flow and methodologies used in the designing
• Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager as per known skills

Additional Comments:
Responsibility- Primary responsibility includes I/O, Macro Characterization, EDA View generation (Functional, Electrical and Physical) & Full package validation. He/she needs to be in constant contact with IP design experts to understand the IP design (schematic, Layout) & IP specification (more electrical characteristics and functional aspect). Must have skills: o Excellent understanding of digital design concepts and CMOS fundamentals. o Ability to quickly comprehend the functional and electrical specifications of custom/full custom IPs. o Proficient in IO/Standard cells/Memory characterization flow using industry-standard tools such as Kronos, Liberate, and Silicon Smart. o Strong understanding of various formats of liberty files, including NLDM, CCS, and LVF. o Skilled in custom layout and schematic design/updates. o Experienced in IP physical model generation (LEF, sign-off GDS, CDL) and conducting validation checks (DRC, LVS, ERC) with debugging skills. o Proficient in behavioral modeling using Verilog/SystemVerilog and testbench writing. o Experience in IBIS (Input/Output Buffer Information Specification) modeling is a plus. o Excellent team player who is disciplined, adaptable, and possesses strong communication skills. Qualification & Experience o B. Tech / M. Tech - Electronics/VLSI Engineering o 3 to 7 years of professional experience in EDA/CAD View generation domain. o Prior ST experience even as intern is preferred.
Skills:
CAD Design engineer,Standard Cell,Cmos
About Company:
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world's best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients' organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact--touching billions of lives in the process.