Job Description

5 - 7 Years
1 Opening
Bangalore

Role description

Client Job Title:

SOC Design Verification Engineer

UST Job Title:

Technical Lead II - VLSI

Location:

Who we are:

At UST, we help the world's best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in over 25 countries, we build for boundless impact--touching billions of lives in the process. Visit us at .

The Opportunity:

We are seeking a highly motivated and experienced SoC Verification Engineer to join our team. As a key member of the verification team, you will be responsible for developing and executing verification plans for complex System-on-Chip (SoC) designs. You will work closely with design and architecture teams to ensure the quality and reliability of our products.

Key Responsibilities:

Perform functional and performance verification of SoC designs using simulation, emulation, and formal verification techniques. Develop and execute comprehensive tests for functional verification and performance verification at the core and SOC level. Create and maintain verification environments using industry-standard tools and methodologies (e.g., UVM). Develop test benches, test cases, and coverage models using UVM, SystemVerilog, and C++. Debug and analyze simulation results to identify and resolve design issues. Collaborate with design and architecture teams to understand design specifications and identify potential verification challenges. Document verification results and track progress. Participate in code reviews and contribute to the improvement of verification methodologies.

Required Skills:

Strong understanding of digital design principles and SoC architecture.

Proficiency in hardware description languages (e.g., SystemVerilog, Verilog, VHDL).

Proficiency in scripting languages (Python) and C/C++

Experience with verification methodologies (e.g., UVM, OVM, VMM).

Experience with simulation tools (e.g., Synopsys VCS, Cadence Xcelium, ).

Experience with debugging and analyzing simulation results.

Strong problem-solving and analytical skills.

Excellent communication and teamwork skills.

Prior experience to industry standard protocols such as AXI, AHB, PCIe, DDR etc. will be an advantage

Desired Skills:

Experience with soc level functional and performance verification. Familiarity with formal verification techniques is a plus. Experience in hardware validation or embedded test automation Experience with scripting languages (e.g., Python, Perl).

Qualification:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

5+ years of experience in SOC design or verification.

Familiarity with hardware description languages (e.g. System Verilo, VHDL, Verilog).

What we believe:

Humility:

We listen, learn, and help selflessly in our interactions

Humanity:

We use business to improve lives

Integrity:

We honor commitments and act responsibly in relationships

Equal Employment Opportunity Statement:

UST is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

Skills

vlsi design,system verilog,asic verification,soc architecture,amba protocol

About UST

UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world's best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients' organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact--touching billions of lives in the process.