Job Description

5 - 7 Years
4 Openings
Bangalore

Role description

SoC level verification using
UVM, Verilog, SystemVerilog, C/C++.
Develop UVM-based frameworks,
automate workflows, improve simulation efficiency.
Knowledge of graphics pipeline,
SystemC/TLM, scripting (Perl, Ruby, Shell).
Leadership/mentorship exposure
preferred.
Sub-system level verification,
MAC/Ethernet experience will be added advantage.
NoC based verification, can be
Sub-system/SoC level verification.

Skills

firmware,uvm,verilog,systemverilog,

About UST

UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world's best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients' organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact--touching billions of lives in the process.