Job Description

Responsibilities

Define and implement the DFT architecture, flow, and methodology for complex SoCs, including scan insertion, MBIST, boundary scan, and IP testing. Analyse digital DFT metrics to evaluate test time, yield, and defect rates. Collaborate with RTL designers, physical design, and verification teams to ensure seamless DFT integration and timing closure without impacting SoC performance. Provide guidance to digital design engineers on designing testable functional modules. Generate and validate manufacturing test patterns (ATPG, BIST). Optimize test coverage and test time for production efficiency. Support silicon bring-up and failure analysis using diagnosis tools. Document DFT methodology and contribute to process improvements.

Experience & Skills

Master's degree in Electrical Engineering, Computer Engineering, or a related field. 5+ years of hands-on experience in DFT implementation and methodology for ASIC/SoC designs. Practical experience with ATPG, BIST, ECC, and redundancy techniques. Strong understanding of digital design, synthesis, STA, and verification flows. Proficient with Siemens Tessent tools (Scan, MBIST, LogicBIST, Diagnosis). Familiarity with scripting languages such as TCL, Python, and Perl. Excellent communication skills and ability to work in cross-functional teams. Strong analytical and problem-solving abilities. Team player with a proactive mindset and critical thinking skills. Fluent in English, both written and spoken.
Job Types: Full-time, Contractual / Temporary

Pay: ₹1,540,960.02 - ₹3,551,514.37 per year

Work Location: In person