Job Description

This position will work within IPG EAIG ESIP team which develops soft IP's in RTL and associated collaterals for Intel latest chipset and SOC products. The responsibilities will include (but not limited to): - Register Transfer Level (RTL) coding, simulation and emulation of IPs and functional units for inclusion in sub-system and downstream SoC or chipset designs. - Performs IP sub-system integration in to hybrid platform, supporting SoC and other stakeholders and represents the Soft IP / validation teams. - Participates in the development of Architecture and Microarchitecture specifications for IP. - Defines and implements verification procedures (or test plans) for IP/Subsystem Hardware product based on features, requirements, and failure points. - Creates initial product verification methodology, selecting the verification strategy, identify failure points and developing test plans. - Develops verification/validation environment and collaterals such as testbenches, stimulus/sequences, checkers, assertions, and coverage. - Performs tests regression, collects and analyzes regression results, root-causes and resolves regression failures. - Provides technical direction, guidance and support to the IP/Subsystem development team and stakeholders throughout the IP/Subsystem and customer's Product Life Cycle. - Influences on product development execution efficiency and quality through continuous improvement on verification methodologies and strategies used across product families. - Retrospect and explores new verification/validation methodology or flow to improvise on existing ones
Qualifications

- The applicant should have a Master or Bachelor degree in Electrical and Electronics or Computer or equivalent Engineering or higher, and at least about 6 years of experience with IP/SoC design or verification development - Familiarity or experience in RTL design with Verilog and System Verilog is required. - Expertise in integration of design blocks (IP) for system-on-chip (SoC) components. - Knowledge of Python, familiarity with Objected Oriented programming, Perl, C++ shell or other scripts is a plus. - Strong analysis, debugging skills, and creative in problem solving. - Familiarity or experience with RTL verification, tools/flow/methodologies and timing analysis/closure is required. - Knowledge of debugging Virtual Platform / RTL model - Hybrid environment - VCS simulation / emulation waveform debug (mandatory) - Knowledge of working with trackers - Identify the debug needs and debug the failures - Knowledge in IPs like I2C, I3C, SPI, UART, etc. is preferred. Knowledge of PCIe or SPI or eSPI is a strong plus. - Knowledge of Power management is preferred. - Knowledge of considerations for performance, power, and cost optimization is desirable. - Knowledge of system boot flow + FW - Demonstrate excellent Self-motivation, communication, strong problem solving, and teamwork skills. - Set aggressive goals and meet/beat the commitments. - Flexible enough to work in a dynamic environment and multitask seamlessly. - Ability to work independently and in a team. - Motivated to learn and adapt to fast-evolving technologies and environments. Passionate for design/tools and methodology - Someone who wants to make a difference through technology while having FUN. Additional Qualifications (EVEN BETTER): - Experience in any of these design tools and methodologies: - System Verilog (OVM/UVM) - Scripting (Python/Perl/Shell) - Experience in PCI Express, SPI/eSPI, AXI would be added value - RTL simulators - Interactive debugger - RTL model build - Testbench development - Power-aware simulation - Coverage-based random constraint simulation. - Experience in any of these areas: = Power Management = Any industry standard device OR interface protocol. Inside this Business Group
IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.
Work Model for this Role

This role will require an on-site presence.
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